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User Testbench
Once configured, the testbench will perform the sequence of tests in Table 8-4 . If the core configuration, as set in
CoreConsole, does not support the required function, the test will not be performed.
Table 8-4 · User Testbench Test Sequence
Test
0
1
2
3
4
5
Required Core
Parameters
Target = 1
Target = 1
Bar0_ENABLE = 1
Target = 1
Bar0_ENABLE = 1
TARGET = 1
MASTER = 1
BAR0_ENABLE = 1
TARGET = 1
MASTER = 1
BACKEND = 1
BAR0_ENABLE = 1
TARGET = 1
MASTER = 1
BACKEND = 1
BAR1_ENABLE = 2
Description
PCI device and vendor IDs are verified and the configuration space initialized.
Single-cycle Target write and read cycle to BAR 0.
Burst Target write and read cycle to BAR 0.
DMA transfer test initially from BAR 0to the PCI bus (the simple Target). The DMA access is
initiated by the testbench using the PCI Master to write to the DMA registers. A second DMA
transfer is then performed to move the data back from the PCI bus to a different location in
BAR 0. Finally, the resultant data is verified.
DMA transfer test initially from BAR 0 to the PCI bus (the simple Target). The DMA access
is initiated by the testbench writing to the DMA registers using the backend interface. A
second DMA transfer is then performed to move the data back from the PCI bus to a different
location in BAR 0. Finally, the resultant data is verified.
FIFO test
Initially, the testbench, using the PCI Master, fills up the output FIFO by writing data to
BAR 1. While data is being written, the clock used to move data from the output to the input
FIFOs is disabled; all data remains in the output FIFO. Once all the data is loaded, the
testbench (through the backend interface) programs the DMA engine to move all the data from
BAR 1 to the PCI Target and re-enables the backend clock to move data between the two
FIFOs. As data is moved into the input FIFO, CorePCIF automatically moves the data from
the FIFO to the PCI Target using its DMA engine until the DMA transfer is completed.
While this process is occurring, the rate at which data is moved between the two FIFOs varies,
causing the input FIFO to empty and causing the PCI core to stop the DMA transfer until the
FIFO is non-empty.
When the DMA transfer is complete, the data in the PCI Target is verified.
Additional verification tests can be run by typing runall.do at the Model Sim prompt. This will invoke the simulation
multiple times using different core configurations (not those set in CoreConsole), and will also enable additional tests.
Customizing the User Testbenches
The user testbenches are intended to be customized by the user. First, the PCISYSTEM module should be replaced by
the actual PCI design being implemented. Once this is done, the test sequence in the main testbench file can be
modified to perform the required configuration and memory cycles. When the simulation is run, the PCI monitor
function will display the PCI activity, and the simple PCI Target can be used as a Target if the unit under test
implements a PCI Master function.
“VHDL User Testbench Procedures” on page 143 and “Verilog User Testbench Procedures” on page 145 list all the
procedure calls using the VHDL and Verilog testbenches. It is recommended that the testbench.vhd (.v) file be read
carefully to fully understand testbench operation.
v4.0
125
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相关PDF资料
COREU1LL-AR
IP MODULE COREU1LL
COREU1PHY-AR
IP MODULE COREU1PHY
CORR-8BIT-XM-UT2
SITE LICENSE IP CORRELATOR XP
CP2-GSA-L
CONN SHIELD LOWER TYPE A 22
CP2-HSA110-1
CONN SHROUD CPCI 2MM TYPE A 22
CP2-HSC055-4
CONN SHROUD CPCI 2MM TYPE C 11
CP2-K3567-SR-F
COMPACT PCI - MISC
CP2105EK
KIT EVAL FOR CP2105
相关代理商/技术参数
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